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    • 专利摘要:
    Methods and apparatus are provided for providing efficient processing of signals in a communication system. Processing of the transmitted signal includes encoding a data block at an encoding rate of 1 / R. The encoding produces R data symbols for every data of the data block. The blocks of RAM 299 and 600 are divided into a number of RAM blocks to enable simultaneous reading of data symbols from the shooter's RAM blocks, producing simultaneous in-phase and quadrature data symbols. At least two scramblers 306 and 307 are used to scramble the in-phase and quadrature phase data symbols simultaneously. Walsh covering / sum block 700 following the scrambler provides efficient Walsh covering and summing of signals for combined transmission from the communication system.
    公开号:KR20030034231A
    申请号:KR10-2003-7004502
    申请日:2001-09-27
    公开日:2003-05-01
    发明作者:니콜라이 슐레겔；제임스 와이. 허트
    申请人:콸콤 인코포레이티드；
    IPC主号:
    专利说明:

    METHOD AND APPARATUS FOR EFFICIENT WALSH COVERING AND SUMMING OF SIGNALS IN A COMMUNICATION SYSTEM}
    [2] Efficient processing of the signal transmitted from the transmitter is one of the next considered performance enhancements in communication systems such as code division multiple access (CDMA) communication systems. Several systems are known, such as CDMA communication systems. One of these systems is a CDMA system that operates based on TIA / EIA-95, commonly known as IS-95, and is incorporated herein by reference. The IS-95 specification provides an operational need and description of the structure of transmission channels, such as forward channels. The forward channels are directed from the base station to one or more mobile stations. In general, forward channels structures corresponding to the IS-95 specification are required to use binary phase shift (BPSK) data modulation and binary pseudorandom number (PN) spreading. The data after the channel encoding is modulated via a BPSK modulator, and a binary PN spreader / modulator spreads the BPSL modulated data symbols by inputting one symbol at a time. In this case, the binary PN spread includes two paths for in-phase and quadrature phase modulation. After summing the carrier modulated signals from each path, the summed results are amplified for transmission from the antenna system.
    [3] Particular requirements for the IS-95 forward channel structures are described in section 7 of the IS-95 standard.
    [4] A communication system, generally known and known as IS-2000 and operating and defined corresponding to the TIA / EIA / IS-2000, incorporated herein by reference, also includes a forward channel structure. The IS-2000 forward channel structure is described in section 3 of the specification. The IS-2000 system is the next version compatible with the IS-95 system. On the forward channel, in addition to the requirement for BPSK modulation for IS-95 compatibility, the IS-2000 system requires QPSK pre-spreading of the data symbols. For QPSK spreading / modulation, the input section of the modulator requires two data symbols at the same time, in phase and quadrature phase data symbols.
    [5] In such systems, there is an increasing demand for efficient processing of signals to reduce processing time and cost. In addition, there is an increasing demand for a method and apparatus for efficiently processing data symbols of a transmitter for transmitting a forward channel signal in a CDMA communication system.
    [1] The present invention relates to the field of communications. More specifically, the present invention relates to a new and improved method and apparatus for a code division access communication system for fast processing of transmission signals.
    [7] The features, objects, and advantages of the disclosed embodiments are described in more detail below in conjunction with the drawings, wherein like reference numerals refer to like elements.
    [8] 1 illustrates several processing blocks of a communication system transmitter.
    [9] 2 illustrates a partitioned RAM structure for interleaving operation of a transmitter in a communication system.
    [10] 3 illustrates several processing blocks of a transmitter of a communication system including at least two scramblers.
    [11] 4 shows a general block diagram of a communication system.
    [12] Figure 5 illustrates Walsh covering, summing, PN spreading and carrier modulation blocks of the transmitter.
    [13] Figure 6 illustrates a partitioned RAM structure for interleaving operation of several channels in a transmitter of a communication system.
    [14] Figure 7 shows scrambling, Walsh covering and summation for several channels at the transmitter.
    [6] The present invention relates to a method and apparatus for efficient processing of signals in a communication system. In-phase and quadrature phase data symbols are produced after the encoding process to perform efficient processing of the signal. Partitioning the RAM structure makes it easy to simultaneously produce data symbols in phase and quadrature. At least two scramblers are used to simultaneously receive and scramble the in-phase and quadrature data symbols. The Walsh Covering / Summing block provides efficient Walsh covering and summing of signals for combined transmission from the communication system.
    [15] New and improved methods and apparatus for efficient signal processing in communication systems are disclosed. The example embodiments described herein describe a digital cellular telephone system environment. While it is preferred to use in such an environment, other embodiments may be incorporated into different environments and structures. In general, the various systems described below may be formed using software control processors, integrated circuits or discrete logic. The data, instructions, commands, information, signals, symbols and chips mentioned throughout the application may preferably be expressed in terms of voltage, current, electromagnetic waves, magnetic fields, light fields or combinations thereof. In addition, the blocks shown in each block diagram may be represented in hardware or method steps.
    [16] Referring to FIG. 1, a simplified block diagram of the forward channel structure 100 is shown. The forward channel structure 100 may be used in a CDMA system operating in accordance with the IS-2000 standard. Channel data bits are input to channel encoder 101 to produce encoded channel data symbols. The function of the channel encoder 101 may include summing frame quality bits and performing convolution and / or turbo encoding. The channel encoder 101 delivers the channel encoded symbols to the block interleaver 102 to interleave the function. The interleaved data symbols can be input to the long code scrambling / modulator block 103, where the data symbols of the respective channels are scrambled with the long code mask. Other functions, such as power control symbol puncturing, may occur in long code scrambling / modulator block 103. De-multiplexer 104 de-multiplexes the output of the long code scrambling / modulator block 103 to generate data symbols for QPSK PN spreading. Since QPSK PN spreading is used, two symbols are output simultaneously by each clock cycle from de-multiplexer 104. QPSK spreading block 105 modulates and spreads the input data symbols for continuous amplification and transmission from an antenna system (not shown).
    [17] The QPSK spreading block 105 operates on at least two data symbols when at least two data symbols are input by every clock cycle. The interleaver 102 and the long code scrambling / modulator block 103 output one data symbol every clock cycle. As a result, the de-multiplexer 104 needs to accumulate data symbols to output two data symbols every clock cycle. As such, processing of the "bottle neck" may be generated at the input of the QPSK spreading block 105, resulting in inefficient processing of the forward channel signal for transmission.
    [18] Referring to FIG. 2, the data block 201 transmitted in the communication system may be encoded at an encoding rate of 1 / R. The encoding may be performed by the channel encoder 101 as described. The encoding rate may be 1/2, 1/4 or other encoding rate. After encoding, the number R of data symbols is produced for every encoded data bit. As a result, the number R of data blocks is generated. In case of encoding at a speed of 1/2, two data blocks are produced at the output of the encoder. The channel structure may also include a block interleaver, such as block interleaver 102. The block interleaver receives two data blocks and, when encoding at a quarter speed, receives four data blocks. The block interleaver 102 inputs each data block, and while rewriting the data in the RAM block, rearranges the positions of the data symbols of the data block corresponding to an interleaving function, and replaces the rearranged data block with the RAM block. Is output from
    [19] In order to efficiently process data symbols in the block interleaver 102, a RAM block may be divided into two RAM 202 and 203 blocks. Data symbols of the received data blocks are written to RAM blocks 202 and 203. The order in which the data symbols are written and their respective positions in the RAM 202 and 203 correspond to certain interleaving functions. Exemplary interleaving functionality can be found in the IS-2000 or IS-95 specification. To output interleaved data symbols, the data symbols from each data block are read sequentially. The sequential read starts at a first RAM block of the two RAMs 202, 203. The sequential read continues in a second RAM block of the two RAMs 202, 203. The sequential read ends in a second RAM block of the two RAMs 202 and 203. The first and second RAM blocks are RAM blocks 202 and 203, respectively.
    [20] Read and write functions may be performed simultaneously on the first and second data blocks associated with the first and second data frames, respectively. The write function is associated with the first data frame when the read is associated with the second data frame. For transmission from the communication system, the first data frame precedes the second data frame. The read and write functions each occur simultaneously in two sets of RAM blocks. Each set contains two RAM blocks. The first set 298 may include RAM blocks 202 and 203, and the second set 297 may include RAM blocks 204 and 205. Data symbols in the second set are written before writing the data symbols in the first set. By retaining the two sets, the write and read records can be changed between the first and second sets. By doing so, simultaneous writing and reading functions can always be generated.
    [21] Each RAM block, such as RAM blocks 202-05, may be partitioned to include at least one pair of RAM subblocks. The RAM subblocks are subblocks 212-13 for RAM block 202, subblocks 214-15 for RAM block 203, subblocks 216-17 for RAM block 204, The subblocks 218-19 for the RAM block 205 are shown. One of each pair of RAM subblocks is stored as in-phase data symbols and another is stored as quadrature phase data symbols. The in-phase and quadrature phase data symbols are stored in subblocks, respectively. The location of each data symbol is determined corresponding to the interleaving function. Sequential reading of the data symbols may include reading the RAM subblocks simultaneously. As a result, in each read step, in-phase data symbols and quadrature phase symbols are produced simultaneously by each clock cycle. For example, referring to RAM block 204, the read function allows reading data bits at each RAM location from sub blocks 216 and 217. Since in-phase and quadrature phase data symbols are stored in sub-blocks 216 and 217, respectively, in-phase and quadrature phase data symbols are simultaneously written and read out.
    [22] Producing in-phase data symbols and quadrature phase data symbols by one clock cycle at the same time is efficient and beneficial for the QPSK spreader, which requires in-phase data and quadrature phase data symbols at its input, and communicates. A chain of signal processing blocks of a transmitter of a system. When the data symbols are processed two for the QPSK spreader at the same time, "bottleneck" processing is not generated as described. As a result, signal processing of the signal is performed efficiently at the transmitter.
    [23] Referring to FIG. 3, an example block diagram of a transmitter 300 for processing a signal is shown. The transmitter 300 is suitable for transmitting CDMA signals, such as forward channel CDMA signals. The transmitter 300 includes a channel encoder 301 for encoding channel data. Examples of such encoders for various channels are described in other similar standards such as the IS-2000 standard and the WCDMA standard. The channel encoder 301 may perform convolutional encoding, turbo encoding symbol addition, and repetition. The input data bits are encoded to produce encoded data symbols. The data bits and data symbols are terms that can be interchanged with each other. One data symbol depending on the modulation and encoding scheme may be represented by several data bits. Based on the encoding rate, encoder 301 generates a number of data symbols for every input data bit. Several encoding speeds are possible. For example, encoding speeds 1/2, 1/4, 1/3 and 1/6 can be used in systems operating in accordance with the IS-2000 standard. In the case of encoding rate 1/2, two data symbols are generated for every input data bit, and in the case of quarter encoding speed, four data symbols are generated. When a data block such as data block 201 is input to encoder 301, two data blocks are generated for encoding rate 1/2, and four data blocks for encoding rate 1/4.
    [24] Encoded data symbols pass through block interleaver 302 for data block interleaving. Basic operation of the interleaver is known in the art. Data symbols input to the interleaver 302 are rearranged corresponding to the interleaver function. The interleaved data symbols are output. For the QPSK spreader 310 in the chain of signal processing blocks of the transmitter 300, it is advantageous and efficient to generate in-phase data and quadrature phase data symbols at the output of the interleaver 302 simultaneously by one clock cycle. When multiple data symbols, eg, in-phase data symbols and quadrature phase data symbols for the QPSK, are processed at the same time, no processing “bottleneck” is generated. The process described with respect to the RAM blocks 202-203 and / or 204-05 may be used to simultaneously generate in-phase and quadrature phase data symbols. Interleaver 302 may also include similar RAM structures.
    [25] Prior to QPSK expansion, encoded data symbols need to be scrambled corresponding to the long code assigned to each channel and / or user channel. Scramblers are known and are known in the IS-2000 standard. Long code scrambling of data symbols includes generating a long code. Long code generator 303 may be necessary to perform long code generation. Since the block interleaver 302 simultaneously produces in-phase data symbols and quadrature phase data symbols, the long code generator 303 simultaneously produces two long code bit streams 304 and 305. Long code stream 304 may be used to scrub in-phase data symbols in I-scrambler 306, and long code stream 305 may be used to scramble quadrature phase data symbols in Q-scrambler 307. The in-phase and quadrature phase data symbols are passed to an I-scrambler 306 and a Q-scrambler 307 that perform data scrambling operations, respectively, to generate scrambled in-phase and quadrature phase data symbols 311 and 312, respectively. .
    [26] The difference between the I and Q scrambling operations is in the long code stream for the scrambling operation. The long code streams 304, 305 are generated by the long code generator 303 at different tap outputs. The I mask and the Q mask can be used to generate the long code generators 304 and 305, respectively. The long code stream 305 precedes the code stream 304 by as long as a fixed or variable code corresponding to the mask being used. For example, long code stream 304 may precede long code stream 305 by 64 code symbols. The long code generator 303 internally generates a long code constituting a stream of code symbols. The stream of code symbols is tapped at different points, for example 64 symbols apart, to produce long code streams 304 and 305. The in-phase data symbols are scrambled in I-scrambler 306 via long code stream 304 and quadrature phase data symbols are scrambled in Q-scrambler 307 via long code stream 305. Scrambled personal and quadrature data symbols 311 and 312 are produced simultaneously. The scrambled in-phase and quadrature phase data symbols are simultaneously sent to QPSK spreader 310 for spreading corresponding to the QPSK spreading structure. Thus, processing of the transmitted signal at the transmitter 300 is performed efficiently.
    [27] Operation of the diffuser 310 may include Walsh cover operation prior to QPSK diffusion. Each user or channel has its own Walsh cover. The operation of the Walsh cover is known and one or more examples are described in the IS-2000 standard. After QPSK magnification, the resulting signal generates a spread spectrum signal 313 transmitted through the carrier modulation and transmitted from the communication system.
    [28] The efficiency of the processing of the transmitted signal is improved when data symbols for one frame are read and data for another frame is written in the interleaver block 302. To facilitate the writing of data symbols for one data frame, block interleaver 302 may include a block of RAM 299, as shown in FIG. The RAM block 299 may be divided into two RAM block sets 297 and 298. Each set may include two RAM blocks. In the case of RAM set 298, RAM blocks 202 and 203 are shown, and in the case of set 297, RAM blocks 204 and 205 are shown. RAM blocks 202-05 may be thought of as part of the larger RAM block 299. For writing data symbols of the first data frame, data symbols are written to a first set of the two RAM blocks 297 and 298. The recording may correspond to some interleaving function. For reading the data symbols of the second data frame, the data symbols are read sequentially from a second set of the two RAM set blocks 297, 298. The first set may be once the set 298 or next the time set 297. Similarly, the second set may be the set 297 once and / or the time set 298 next. Thus, while the data is written in one set, the data is read from another set.
    [29] The read operation is performed sequentially at each RAM location. For example, in RAM set 297, the sequential read starts at RAM block 204, which is the first RAM block of two RAMs 204 and 205, for example, two RAM blocks 204 and 205 ) Is a second RAM block, for example, in RAM 205. The sequential read ends at the second RAM block 205 of the two RAM blocks 204 and 205 of the RAM set 297. In RAM block 299, each block of RAM is divided into at least two RAM subblocks for storing in-phase data symbols and quadrature phase data symbols. In each read step, two data symbols are read, one in phase and the other in quadrature. Two RAM sub-blocks are read simultaneously in the sequential read step, and generate in-phase data symbols and quadrature phase data symbols simultaneously. The in-phase data symbol and quadrature phase data symbol are simultaneously input to the I-scrambler 306 and the Q-scrambler 307 respectively, which improves the efficiency of the transmission signal processing.
    [30] The RAM structure 299 may include a write pointer (not shown for simplicity) in which data symbols are written to a first set of two RAM blocks. The operation of the write pointer in a RAM structure environment is known in the art. The write pointer may be programmed to write input data symbols corresponding to a predetermined interleaving function used in the block interleaver 302. In addition, the RAM structure 299 may include a read pointer for reading sequential data bits. If the read action occurs, for example, for the set 297, the read pointer sequentially begins to read in the RAM block 204 and continues in the RAM block 205. The read pointer terminates reading of data symbols in RAM 205. Each RAM block of the two RAM blocks in sets 297 and 298 includes at least two RAM subblocks. Through the write pointer, one of the two RAM subblocks stores in-phase data symbols and another stores quadrature phase data symbols. Through the read pointer, the two RAM subblocks are read simultaneously in the sequential read step to produce in-phase data symbols and quadrature phase data symbols simultaneously.
    [31] 4, a block diagram of an exemplary communication system 400 is shown. The communication system 400 includes a base station 410 connected to a terrestrial network 401. A land-based network (401) provides a ground connection to a user in the communication system 400, such as a landline connection and a data network connection. Base station 410 may also be connected to other base stations (not shown for simplicity). Wireless users of communication system 400 may be several mobile stations, such as mobile stations 451-53. Although only three mobile stations are shown, there may be several mobile stations in communication system 400 depending on the system capacity at all times. The mobile stations maintain a communication link with the base station to receive and transmit information such as voice information or data information. The communication link between base station 41 and each mobile station may include a forward link from the base station 410 to mobile stations and a reverse link from each mobile station to the base station. Various structures for the reverse and forward links are described in the IS-95, IS-2000 and WCDMA specifications. Base station 410 may be integrated with transmitter 300 for transmission of the forward link paths.
    [32] On the forward link, the channel data bits are sent to channel encoder 301. The channel data may be generated by the terrestrial network 401 or other possible source. Channel data for one or more receiving users is generated and transmitted to the channel encoder 301. Encoded data symbols are sent to a block interleaver 302 that interleaves the data symbols for each channel corresponding to the interleaving function. Because channel encoder 301 encodes channel data for one or more channels, block interleaver 302 may receive encoded data symbols associated with one or more channels on the forward link communication. Interleaved data symbols pass through long code that performs the scrambling operation as disclosed. Each channel can be assigned a long code. The interleaved data symbols for each channel are transmitted via the associated long scrambling operation on the forward link. The long scrambled data symbols for each channel are sent to QPSK spreader 310 to form a combined forward link signal. In particular, the advantageous aspects of the various disclosed embodiments become more apparent when using the forward link. Thus, when several forward link channels are combined in the forward link signal, the block interleaver 302 can be made in accordance with several published embodiments for efficient processing of the signals in the forward link direction. Referring to Figure 5, a block diagram of a QPSK diffuser 310 is shown. The operation of the QPSK spreader 310 is shown as shown, the Walsh cover operation to generate a signal 313 amplified from the base station 410 to mobile stations in the coverage area, the signals of each forward link channel Summing operation, complex multiplier operation, baseband filtering operation and carrier modulation operation. QPSK diffuser 310 may include some operation in various structures. In general, Walsh codes are assigned to each channel in the direction of the meniscus link. After long code scrambling, the resulting I and Q signals are passed through Walsh cover operation. The Walsh cover operation for the channel is shown in Walsh cover block 510. Walsh cover operation of block 510 includes multiplying the input I and Q signals 311, 312 by the assigned Walsh function to generate Walsh covered I and Q signals 506, 507.
    [33] If there are other channels coupled on the forward link, the I and Q signals 541, 542 of the other channels are Walsh by respective Walsh codes, such as the Walsh cover operation of the Walsh cover block 510. After being covered, it is input to diffusion blocks 543, 544. Prior to the Walsh cover operation, the I signals 541 and Q signals 542 were encoded for the long code scrambling shown for encoding and block interleaving operations and the I signals 311 and Q signals 312. Passed through long code scrambling operations similar to operations. After the Walsh cover operations, I signals 506 and 541 are summed in summing block 543 and Q signals 507 and 542 are summed in summing blocks 544. The results are Q-signals 546 combined with I-signal 545 combined.
    [34] The next operation of the QPSK spreader 310 includes a composite multiplier operation 570 via a PNI sequence 547 and a PNQ sequence 548. PNI and PNQ sequences 547 and 548 are I and Q channel PN sequences. The combined I and Q signals 545 and 546 are complex multiplied by PNI and PNQ sequences 547 and 548. The complex multiplier operation 570 includes spreading signals 545 and 546 and generates I and Q signals 571 and 572. Baseband filters 573 and 574 can be used to filter the I and Q signals 571 and 572. After filtering, multipliers 575 and 576 are used for carrier modulation I and Q signals 571 and 752. The resulting signals are combined at combiner 577 to produce combined signal 313. Signal 313 is amplified for transmission from one or more antennas of base station 410.
    [35] Referring to Figure 6, to provide efficient interleaving operation involving one or more forward channels coupled on a forward link signal, RAM structure 600 is divided into a number of RAM blocks, such as RAM blocks 601-03. do. Although only three divided blocks are shown, other numbers of divided RAM blocks are also possible. Each of the RAM blocks 601-03 is divided into two sets of RAM blocks. For example, the RAM block 601 is divided into two sets 610, 611 of RAM blocks, similarly a set 620, 621 for the RAM block 602 and a set for the RAM block 603. 630, 631. In addition, each set contains two blocks of RAM. For example, the set 610 includes RAM blocks 610 and 613, and the set 611 includes RAM blocks 614 and 165.
    [36] RAM blocks 601, 602 and 603 are each connected with a channel of the forward link. Each of the plurality of RAM blocks 601-03 includes data associated with a channel. To store data, data symbols are written to the first set of two RAM block sets. In the case of the RAM block 601, the first set may be a time set 610 once and the other time set 611. Recording data corresponds to a predetermined interleaving function. To read the data for each of the plurality of RAM blocks 601-03, a read pointer sequentially reads data symbols from a second set of two sets of RAM blocks. In the case of the RAM block 601, the second set may be a time set 610 or another time set 611. When data writes occur in the first set, data reads occur in the second set. Writing data to each of the plurality of RAM blocks 601-03 may occur simultaneously. In addition, reading data from each of the plurality of RAM blocks 601-03 may occur simultaneously.
    [37] Sequential reading of each of the plurality of RAM blocks 601-03 begins with the second set of first RAM blocks. For example, if the second set is set 611, the sequential read of data begins at RAM block 614. The sequential read continues in the second set of RAM blocks, ie RAM block 615 in the illustrated example. The sequential read ends at the second set of RAM blocks, ie RAM block 615 in the illustrated example.
    [38] For each of the plurality of RAM blocks 601-03, each of the two RAM blocks in each set is divided into at least two RAM sub blocks. One of the two RAM subblocks stores in-phase data symbols and other quadrature phase data symbols via the read process. The RAM subblocks are read simultaneously at each stage of the sequential readout to produce in-phase symbols and quadrature phase data symbols simultaneously. Thus, during reading data from the plurality of RAM blocks 601-03, in-phase and quadrature phase data symbols are produced simultaneously from each of the RAM blocks. Thus, in-phase and quadrature phase data symbols associated with three forward channels corresponding to the plurality of RAM blocks 601-03 are produced simultaneously. At the same time producing the data symbols improves the processing efficiency of the transmission signals.
    [39] Each set of RAM has data bits for one data frame. For example, RAM set 610, which consists of RAM blocks 612 and 163, has data to fill one data frame. Since the RAM blocks 601, 602, 603 are each associated with the channel of the forward link, respectively, each block has data written and read for each channel. For example, for each channel, data is read from set 611 while data is written to set 610. Similarly for other channels of other RAM blocks, while data is written in one set of RAM blocks, data is read from another set of the same RAM block.
    [40] Each data frame of each channel has a fixed number of data bits. Thus, the read operation of the RAM blocks 601, 602, 603 can be simplified. For example, if read point 691 reads data from a RAM location in RAM set 611, read pointer 692 is pointed to another RAM location in set 621. The read pointer 692 is always in a fixed relationship with respect to the position of the read pointer 691. For example, if the read pointer 691 is pointed to the first RAM location of the set 611, the read pointer 692 is pointed to the first RAM location of the set 621. The fixed offset between the read pointers 691 and 692 is equal to the size of a RAM block, such as RAM blocks 601, 602. Since the RAM structure 600 is divided into multiple RAM blocks having the same number of RAM locations, such as RAM blocks 601-03, the offset between different pointers also remains the same. Thus, the read operation for all the blocks may use one read offset for all read pointers, such as read pointers 691-93. Thus, reading data from the RAM blocks 601-03 can be simplified with processing minimized to the calculation of read pointer positions for each RAM blocks.
    [41] The RAM structure 600 may be divided into a certain number of RAM blocks having the same number of RAM locations. The number of RAM blocks of the RAM structure 600 is equal to the number of channels processed by an integrated circuit that regulates channel interleaving operations in the system. For simplicity, three RAM blocks 601, 602 and 603 are shown corresponding to three different channels, although other numbers of RAM blocks corresponding to the same number of channels are possible. The three read pointers 691, 692, 693 correspond to the three different channels. To adjust the processing of block interleaving for all three channels, read pointers 692 and 693 are set in fixed increments from read pointer 691. As a result, operation control of the RAM structure 600 only needs to adjust one read pointer by a number of fixed offsets. The simplicity allows for efficient processing of interleaving operations in multichannel systems.
    [42] Referring again to Figure 4, base station 410 also transmits pilot channels received by all mobile stations in the coverage area. Operation of pilot channels is known and described in IS-95, IS-2000 and WCDMA specifications. A pilot channel is sent to the mobile station to assist the mobile station in determining the characteristics of the propagation channel. The pilot channel information is used to decode other channels such as traffic channels, paging channels and other control channels. The frame timing of each forward link channel may be oscillated relative to the frame timing measured from the pilot PN sequence. This is commonly referred to as frame offset. Frame offset is performed to prevent large power fluctuations of the forward link signal. Although several forward link channels have a general frame offset, different forward link channels can be assigned different frame offsets. Pilot channel PN sequence 430 may be repeated every 26.6 msec. The forward link frame offset is measured from the beginning of pilot channel PN sequence 430. For frame time offset 431 (frame offset "0"), the start of the frame coincides with pilot channel PN sequence 430. For frame time offset 432 (frame offset " 1 "), the start of the frame is time offset by a certain number of chips from the start of pilot channel PN sequence 430, possibly equal to 1.25 msec. For frame time offset 433, frame offset " 2 ", the start of the frame is time offset by a predetermined number of chips from the start of pilot channel PN sequence 430, possibly equal to 1.25 msec. One frame of the forward link may be equal to 20 msec. Thus, there may be 16 possible frame time offsets, each time offset equal to 1.25 msec from the immediately following time offset, before the start of the frame offset coinciding with the start of another frame offset. One or more channels may use the same frame offset.
    [43] RAM blocks 601-03 may correspondingly be associated with three different channels. The channels may use different frame offsets, for example frame offsets 431-33. The channels corresponding to the RAM blocks 601-03 may have frame offsets 0, 1, and 3, respectively. Thus, writing data to each block shifts correspondingly to the time offsets. To illustrate with reference to Fig. 6, RAM blocks 601-03 are shown in hatched portions. The hatched portions indicate the RAM location where data can be written at a given time. For example, in RAM block 601, the hatched portion occupies RAMs 612 and 613 starting in RAM 612 and ending in RAM 613. If the channel associated with RAM block 602 is at time offset "1" and time offset "1" is at a time offset of 1.25 msec, the beginning of the hatched portion of RAM block 602 portion is a data frame. Is shifted by the number of RAM locations equal to the number of data symbols occupying 1.25 msec. The hatched portion is correspondingly shifted from set 620 to set 621 by the same amount. If the channel associated with RAM block 603 is at time offset "2" and time offset "2" is at a time offset of 1.25 msec, the beginning of the hatched portion of RAM block 603 portion is a data frame. Is shifted by the number of RAM locations equal to the number of data symbols occupying 2.5msec.
    [44] Since the read pointers 691-93 point to the same position in each of the RAM blocks, the data output for each channel is eventually shifted by the same amount of time as the frame time offset. This can be explained in terms of the timing of the data frames 670-72. Data frame 670 with frame offset "0" may be a data frame read from RAM block 601. Data frame 671 with frame offset "1" may be a data frame read from RAM block 602. Note that the beginning of the frame is at a time offset equal to 1.25 msec. Data frame 672 with frame offset “2” may be a data frame read from RAM block 603. Note that the start of the frame is at a time offset equal to 2.5 msec. Thus, when the data is written to the RAM blocks corresponding to the frame offsets, reading the data for data frames having different frame offsets is simplified.
    [45] For data frame 670 with frame offset "0", sequential reading of data begins in RAM 614, continues in RAM block 615, and ends in RAM block 615. For a data frame 671 having a frame offset "1", the sequential read begins at set 621, but the number of data symbols equal to the time offset is ignored or deleted. Sequential reading of the data frame 671 continues in set 620. The sequential read ends at set 621. The number of data symbols read from set 621 is equal to the number of data symbols deleted or ignored in set 620. For data frame 672 having frame offset "2", sequential readout continues in set 631, but the number of data symbols equal to the time offset is deleted or ignored. The sequential readout of the data frame 672 continues at set 630. The sequential read ends at set 631. The number of data symbols read from set 631 is equal to the number of data symbols deleted or ignored in set 630.
    [46] For transmission of a data frame, such as data frame 201, the data frame may be passed through an encoding process at channel echoer 301 prior to the interleaving operation of block interleaver 302. Different encoding speeds are possible. For example, for encoding rates 1/2 and 1/4, two and four data symbols, respectively, are produced for every data bit at the input. BPSK or QPSK spreading follows the interleaving operation. For BPSK spreading, as is known, the Q-leg of the spreading operation is fixed at zero. The IS-95 standard describes the need for the BPSK spreading. This may also be the case for the radio architectures 1 and 2 shown and described in the IS-2000 standard. The radio structures 1 and 2 are provided to the IS-2000 as part of the IS-95 standard. As described in IS-2000, the radio architecture 3-9 requires QPSK spreading. As a result, the operation of communication systems that conform to the IS-2000 specification is required to have BPSK and QPSK spreading. In order to have efficient signal processing, the RAm structure 600 needs to have the capacity to adjust the interface with both BPSK and QPSK spreading.
    [47] The size of each RAM block of the RAM structure 600 is set to eight rows of RAM. The first four columns are assigned to the first set, and the last four columns are assigned to the second set. From the above description that provides efficient processing of the transmission signals, the data is written to the first set while data is read from the second set. For example, RAM block 601 is divided into columns 681-688. The first fourth columns 681-684 form the first set 610, and the last fourth columns 685-688 form the second set 611. Each column is long enough to hold the data bits contained in one data frame 201. Each column may be set to hold 192 data symbols. Each column may be considered a sub-block. Each column can hold in-phase data symbols or quadrature data symbols.
    [48] For BPSK spreading following the interleaver operation, the column allocated to store the quadrature data symbols is filled with data symbols all equal to zero. Thus, when the data symbols are read for BPSK spreading, the quadrature phase data symbols having all zero values are used to affect the BPSK spreading. For example, sub-block 687 may store in-phase data symbols, and sub-block 688 may store quadrature phase data symbols. In the case of BPSK spreading, the data symbols stored in the subblock 688 may be all zeros or the stored data symbols may be ignored and zeros may be replaced in the read operation. The structure of the forward channels corresponding to the radio structure (1, 2) based on the IS-2000 standard requires channel encoding at rate 1/2 with BPSK spreading. In this case, encoding the data bits of the data frame produces the same data symbols as the two data frames, which fill the two sub blocks. For example, if the set 610 is used to write the interleaved data symbols, sub-blocks 681 and 683 are required. The subblocks 682, 684 are filled with zeros or the stored value is ignored during the read operation and the value of zero is replaced.
    [49] In the radio architectures 3 and 5, the encoding rate is 1/4 with QPSK spreading. Thus, the encoder produces the same data symbols as four data frames for one data frame at the input. In this case, if, for example, set 610 is used to write the interleaved data, all the RAM locations of sub-blocks 681-84 are used to store all the interleaved data. The in-phase data symbols are recorded in sub-blocks 681 and 683, and the quadrature phase data symbols are written in sub-blocks 682 and 684.
    [50] In the radio architecture 4, the encoding rate is 1/2, and QPSK spreading is used. In that case, the encoder produces the same data symbols as two data frames for each data frame at the input. Since each set contains four rows of RAM, the encoded data produced in the radio structure 4 is written to four RAM rows while skipping at least some of the RAM locations. For example, while using columns 687 and 688, the encoded data skips RAM locations (1, 3, ... 191) while RAM locations (0, 2, 4, ... 190). , 192). During the read operation, RAM locations 1, 3, ... 191 are ignored. For the QPSK operation, the RAM locations 0, 2, 4, ... 190, 192 in columns 787 and 688 are read out simultaneously for the in-phase and quadrature data symbols, respectively. Thus, the process of calculating the position of the read pointer for different radio structures is simplified.
    [51] It is also desirable to provide efficient transmit signal processing for the Walsh covering and summation operations. The data symbols for each channel pass through the Walsh cover operation to produce Walsh covered data symbols. Walsh cover operations include multiplying the data symbols with Walsh symbols. One Walsh symbol may be several chips, such as 64 chips. Thus, 64 chips are produced for every data symbol. In-phase data symbols and quadrature phase data symbols pass through Walsh covering operations independently as shown in block 510. Walsh covered data symbols of different channels are summed to form a summed signal for transmission of a forward link signal comprising one or more forward channels. The operation of summing in-phase and quadrature phase data Walsh covered symbols is shown in blocks 543 and 544. Therefore, it is desirable to provide efficient Walsh covering and summing operations.
    [52] Referring to FIG. 7, a block diagram of processing block 700 is shown to produce combined Walsh covered signals 545, 546. The operations are the same for generating signals 545 and 546. Signal 545 is represented by an I-signal and signal 546 is represented by a Q-signal. RAM block 600 simultaneously produces the in-phase and quadrature phase data symbols for each channel from RAM sets 601-603. The quadrature phase data symbols are shown at 701-03, and the in-phase data symbols are shown at 711-13. Quadrature phase data symbols 701-03 pass through long code scrambling block 751, respectively, to produce scrambled quadrature phase data symbols 761-63. In-phase data symbols 711-13 pass through long scrambling block 750, respectively, to produce scrambled in-phase data symbols 771-73. Symbols 771 and 761 are associated with the first channel and are assigned Walsh code W0. Symbols 772 and 762 are associated with a second channel and are assigned Walsh code W1. Symbols 773 and 763 are associated with the third channel and are assigned Walsh code W2. Data symbols 771-73 and 761-63 pass through Walsh covering / combining blocks 781-86. Buffer 790 is used to buffer the data symbols, otherwise the data symbols pass directly through.
    [53] Walsh covering / combining blocks 781-83 receive in-phase data symbols 771-73. At block 781, multiplier 791 multiplies data symbol 771 with the assigned Walsh code W0. At block 782, multiplier 792 multiplies data symbol 772 with the assigned Walsh code W1, which is delayed by at least one chip from the time product performed by multiplier 791. . At block 783, multiplier 793 multiplies data symbol 773 with the assigned Walsh code W2, which Walsh code is delayed by at least one chip from the time product performed by multiplier 792. . The Walsh covered data symbol in block 781 is generated one chip ahead of the data symbol in block 782, and the data symbol in block 783 is two chips ahead. Since the Walsh covered data symbols of block 781 are prepared prior to the Walsh covered data symbols of block 782, it is necessary to add up a summer to add up simultaneously with the Walsh covered data symbols produced at block 782. 775). The result is stored in buffer 778. At this point, buffer 778 maintains the sum of the first data symbols produced by blocks 781 and 782. The summed result is prepared with at least one chip before the Walsh covered data symbol of block 783 is produced. The summed results from buffer 778 are passed to summer 776 to sum with the Walsh covered data symbols produced by multiplier 793. The result is placed in buffer 779. At this point, buffer 779 holds a data symbol that is the sum of the first data symbols of the three channels associated with data symbols 711-13. The summed result from the buffer 779 is transferred to the first symbol of the signal 545. Since the data block can hold 192 data symbols, the process is repeated for all other data symbols to produce Walsh covered summed data symbols for signal 545.
    [54] For example, the second data symbol input to block 781 is processed when block 782 processes the first data symbol. As a result, when block 782 processes the second data symbol, block 781 produces the second data symbol in buffer 777 and sums it with the second data symbols produced in block 782. To be delivered. Similarly, when block 783 processes the second data symbol, the Walsh covered second data symbol is prepared, placed in buffer 778, and produced by multiplier 793. The data is passed to a summer 776 to sum with a second Walsh covered data symbol. The result is placed in buffer 779 and used as the second data symbol of signal 545. The process is repeated to produce other data symbols for signal 545.
    [55] Walsh covering / combining blocks 784-86 receive quadrature phase data symbols 701-03. At block 784, multiplier 794 multiplies data symbol 761 by the assigned Walsh code W0. At block 785, multiplier 795 multiplies data symbol 762 with the assigned Walsh code W1, which is at least one chip from the multiplication time performed by multiplier 794. Has a delay. At block 786, multiplier 796 multiplies data symbol 763 by the assigned Walsh code W2, which is at least one chip from the multiplication time performed by multiplier 795. Has a delay. The Walsh covered data symbol in block 784 is generated one chip ahead of the data symbol in block 785, and the data symbol in block 786 precedes two chips. Since the Walsh covered data symbols of block 784 are prepared prior to the Walsh covered data symbols of block 785, it is necessary to add up a summer to add up simultaneously with the Walsh covered data symbols produced at block 785. 765). The result is stored in buffer 768. At this point, buffer 768 maintains the summed result of the first data symbols produced by blocks 784 and 785. The summed result is prepared with at least one chip before the Walsh covered symbols of block 786 are produced. The summed results from buffer 768 are passed to summer 766 to sum with the Walsh covered data symbols produced by multiplier 796. The result is placed in buffer 769. At this point, buffer 769 holds a data symbol that is the sum of the first data symbols of the three channels associated with data symbols 701-03. The summed result from the buffer 769 is passed to the first data symbol of the signal 546. Since the data block can hold 192 data symbols, the process is repeated for all other data symbols to produce Walsh covered summed data symbols for signal 546.
    [56] The second data symbol of the frame data at block 784 is processed when block 785 processes the first data symbol. As a result, when block 785 processes the second data symbol, block 784 produces a second data symbol in buffer 767 and sums it with the second data symbol produced by block 785. To be delivered to. Similarly, when block 786 processes the second data symbol, the Walsh covered second data symbol is prepared and placed in buffer 768, which is passed to summer 766 to send a multiplier ( Summed by the second Walsh covered data symbol produced by 796). The result is placed in buffer 769 and used as the second data symbol of signal 546.
    [57] The operation of block 700 may be performed by an integrated digital circuit. The use of operating clock cycles of digital circuits is known. Thus, the data symbols in buffers 779 and 769 may be produced in at least two clock cycles. One clock cycle for each multiplication in blocks 791-96 and one clock cycle for each summation operation of summers 774-76 and 764-66. Since most digital circuits also use an oversampled clock frequency, the block frequency may be multiple times the chip speed of the Walsh chip used in the Walsh covering operation. The number of combined signals is not limited to three signals as shown in FIG. The process described for the three channels is repeated for as many channels as desired. For example, 64 channels may be involved in the operation of block 700.
    [58] To increase the efficiency of processing the transmission signal on the forward link, the operation of blocks 781-86 should be changed to include feedback, such as feedbacks 720, 721. For example, if there are three or more channels combined on the forward link, blocks 781-86 are different channels until all channels have been combined for the forward link signals 545, 546. Can be used repeatedly for. When one chip is produced every two clock cycles in buffers 779 and 769, three chips associated with the three channels are processed. If the clock cycle is 16 times the chip speed, the process can be repeated eight times for the processing of all 24 chips. Since three blocks 781-83 for the I-channel and three blocks 784-86 for the Q-channel are shown, the processing completed in one chip time results in 21 additional channels. Can be repeated for an additional 21 chips associated with. Thus, blocks 781-86 may be reused to process data symbols associated with the additional channels in one chip time. Thus, the three blocks 781-83 can be used to produce a chip for signal 545 in chip time for Walsh covering and the sum of all 24 channels. The feedback 720 is used to feed back the result of the buffer 779 after every execution upstream that is summed in summer 774 by the newly arriving data symbol. The feedback process is repeated eight times to collect data symbols in the buffer 779, where the data symbols are the sum of all 24 channels. When additional channels are summed, RAM 600 produces data symbols associated with the additional channels. Similar operation is performed by feedback 721. The feedback 721 is used to feed back the result of the buffer 769 after execution of the newly arriving data symbol to every higher sum in the summer 764. To facilitate the process, buffers 722 and 723 are used to collect the chips that make up the data symbol before one data symbol is passed to the signal spreader.
    [59] The previous description of the preferred embodiments has been provided enough to enable those skilled in the art to practice the invention. Many modifications to these embodiments are apparent in the art, and the general principles set forth herein may be applied to other embodiments without inventive capability. Accordingly, the present invention is not limited to the embodiments described below, but is to be construed broadly as corresponding to the novel features disclosed below.
    权利要求:
    Claims (13)
    [1" claim-type="Currently amended] 1. A method of combining Walsh covering in a communication system with summing operations of a plurality of channels each having block data transmitted thereon;
    Walsh covering a first data symbol of a first data block associated with a first channel of the plurality of channels;
    Walsh covering a first data symbol of a second data block associated with a second one of the plurality of channels and the second symbol of the first data block;
    Summing the first Walsh covered data symbol of the first block and the first Walsh covered data symbol of the second block to produce a first cover summed data symbol of the first and second channels. Include,
    Wherein the Walsh covering of the first data symbol of the second channel is delayed by at least one chip from the Walsh covering of the first data symbol of the first data block.
    [2" claim-type="Currently amended] 2. The method of claim 1, further comprising: Walsh covering the third data symbol of the first data block and the second data symbol of the second data block essentially simultaneously;
    Summing the second Walsh covered data symbol and the second Walsh covered data symbol of the first data block to produce a second Walsh covered summed data symbol of the first and second channels. A Walsh covering step and an operation summation step of the multiple channels.
    [3" claim-type="Currently amended] The method of claim 1, wherein the plurality of channels comprises two or more channels,
    Walsh covering a first data symbol of a third data block associated with a third channel;
    Fed back to a summer to sum the first Walsh covered summed data symbol with the Walsh covered first data symbol of the third data block to provide a final first Walsh covered of the first, second and third channels. 31. A method of combining a Walsh covering step and an operational summation of multiple channels further comprising producing a summed data symbol.
    [4" claim-type="Currently amended] The method of claim 1, wherein the plurality of channels comprises three or more channels,
    Walsh covering a first data symbol of a third data block associated with a third channel;
    Feeding back the Walsh covered summed data symbol to a summer to sum with the first Walsh covered data symbol of the third data block to produce a tentative final first Walsh covered summed data symbol;
    Walsh covering a first data symbol of a fourth data block associated with a fourth channel;
    The first data symbol of the fourth data block is summed with the latent final first Walsh covered summed data symbol to be the final first Walsh covered summed data of the first, second, third and fourth channels. Producing a symbol,
    Wherein the Walsh covering of the first data symbol of the fourth channel is delayed by at least one chip from the Walsh covering of the first data symbol of the third data block.
    [5" claim-type="Currently amended] 1. A method of combining Walsh covering in a communication system with summing operations of a plurality of channels each having block data transmitted thereon;
    Walsh covering data symbols of each data block, wherein the Walsh covering corresponding to the data symbols from each block is delayed from a different data symbol;
    While the delayed Walsh covering occurs, summing corresponding Walsh covered data symbols of each block to produce Walsh covered summed data symbols.
    [6" claim-type="Currently amended] 6. The method of claim 5, further comprising reading the corresponding data symbols of the data blocks to produce at least one Walsh covered summed data symbol at essentially the same time. .
    [7" claim-type="Currently amended] 6. The method of claim 5, wherein while repeating summation with the Walsh covering to produce at least one remaining summed Walsh covered data symbol, at least one Walsh covered summed data symbol for dependent QPSK or BPSK spreading. And a Walsh covering step further comprising buffering a plurality of channels.
    [8" claim-type="Currently amended] 6. The method of claim 5, wherein the delay is essentially the same as the at least one chip of the Walsh code used for Walsh covering and the operation summation of the multiple channels.
    [9" claim-type="Currently amended] 6. The method of claim 5, further comprising buffering corresponding data symbols of the blocks for reading.
    [10" claim-type="Currently amended] 1. An apparatus that combines Walsh covering in a communication system with summing the operation of multiple channels having block data on which each channel is transmitted.
    A first multiplier for Walsh covering a first data symbol of a first data block associated with a first channel;
    A second multiplier for Walsh covering a first data symbol of a second data block associated with a second channel;
    A summator for summing the first Walsh covered data symbol of the first block and the first Walsh covered data symbol of the second block to produce a first Walsh covered data symbol;
    Wherein the Walsh covering of the first data symbol of the second channel of the second multiplier is delayed by at least one chip from the Walsh covering of the first data symbol of the first multiplier and the operation of multiple channels. Summing step combining device.
    [11" claim-type="Currently amended] The method of claim 10, wherein the plurality of channels comprises two or more channels,
    The first multiplier performs Walsh covering of a first data symbol of a third data block associated with a third channel,
    A Walsh covering step and an operational summation of the multiple channels further comprising a feedback connection for feeding back the first Walsh covered summed data symbol to the Walsh covered first data symbol of the third data block to a summer Coupling device.
    [12" claim-type="Currently amended] 1. An apparatus that combines Walsh covering in a communication system with summing the operation of multiple channels having block data on which each channel is transmitted.
    A plurality of multipliers for Walsh covering of data symbols of the data blocks, the Walsh covering of corresponding data symbols from each block comprising: a plurality of multipliers delayed from each different data symbol of the plurality of multipliers;
    Wherein the delayed Walsh covering occurs, a Walsh covering step and multiple channels of operation summation step comprising a plurality of adders for summing corresponding Walsh covered data symbols in each block to produce a Walsh covered summed data symbol.
    [13" claim-type="Currently amended] 13. The apparatus of claim 12, wherein the delay is essentially equal to at least one chip delay of the Walsh code used for the Walsh covering.
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    同族专利:
    公开号 | 公开日
    TW510090B|2002-11-11|
    WO2002027959A3|2002-08-29|
    DE60134244D1|2008-07-10|
    WO2002027959A2|2002-04-04|
    EP1320940B1|2008-05-28|
    BR0114239A|2006-09-12|
    AT397327T|2008-06-15|
    US6847677B1|2005-01-25|
    JP2004515093A|2004-05-20|
    AU1129002A|2002-04-08|
    KR100838959B1|2008-06-16|
    US7940832B2|2011-05-10|
    EP1320940A2|2003-06-25|
    CN100474785C|2009-04-01|
    US20050201448A1|2005-09-15|
    CN1541455A|2004-10-27|
    JP4913312B2|2012-04-11|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2000-09-29|Priority to US09/676,346
    2000-09-29|Priority to US09/676,346
    2001-09-27|Application filed by 콸콤 인코포레이티드
    2001-09-27|Priority to PCT/US2001/030417
    2003-05-01|Publication of KR20030034231A
    2008-06-16|Application granted
    2008-06-16|Publication of KR100838959B1
    优先权:
    申请号 | 申请日 | 专利标题
    US09/676,346|US6847677B1|2000-09-29|2000-09-29|Method and apparatus for efficient Walsh covering and summing of signals in a communication system|
    US09/676,346|2000-09-29|
    PCT/US2001/030417|WO2002027959A2|2000-09-29|2001-09-27|Method and apparatus for efficient walsh covering and summing of signals in a communication system|
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